The present invention relates to a CMOS image sensor; and more particular, to a CMOS image sensor having an automatic reference voltage controller, thereby preventing an erroneous correlated double sampling (CDS) operation.
Generally, an image sensor is an apparatus to capture images using light sensing semiconductor materials. The image sensor includes a pixel array which contains a plurality of image sensing elements, e.g., photodiode and receives light from an object to generate an electric image signal.
FIG. 1 is a block diagram illustrating a CMOS (complementary metal oxide semiconductor) image sensor.
Referring to FIG. 1, the CMOS image sensor includes a control and system interface unit 10 for controlling the image sensor by controlling control signals, a pixel array 20 and an analog-to-digital converter 30 for converting an analog image data from the pixel array into a digital image data. Also, the analog-to-digital converter 30 includes a ramp voltage generator 31 for generating a reference voltage with a predetermined slope, a comparator 32 for comparing the reference voltage with the analog image data to generate a digital image data, and a double buffer 40 for storing the digital image data.
The pixel array 20 including Mxc3x97N unit pixels, arranged in a matrix, senses images from an object. The image sensor generally employs a correlated double sampling (hereinafter, referred to as a CDS), to thereby obtain high picture quality under the control of the control and system interface unit 10. In order to implement the CDS, each of the unit pixels includes, e.g., a photodiode and four transistors, respectively. Also, the four transistors in the unit pixel include a transfer transistor, a reset transistor, a drive transistor and a select transistor. According to the CDS, the unit pixel outputs a reset voltage level as a unit pixel output signal from a voltage source by turning on the select transistor while the reset transistor is kept on a turned-on state under the control of the control and system interface unit. Also, the unit pixel provides a data voltage level as another unit pixel output signal from the photodiode by turning on and off the transfer transistor in a turned-off state of the reset transistor and reading out the photoelectric charges generated in the photodiode under the control of the control and system interface unit. As a result, an unexpected voltage in the unit pixel can be effectively removed and a net image data value can be obtained by using the reset voltage level and the data voltage level as unit pixel output signals.
FIG. 2 is a circuit diagram illustrating a CMOS image sensor core. The core circuit includes a unit pixel 200, a comparator 320 and a unit latch circuit 400, and FIG. 3 is a plot illustrating an operation of a comparator and a double buffer shown in FIG. 2. That operation of the image sensor core is disclosed in a copending commonly owned application, U.S. Ser. No. 09/258,448, entitled xe2x80x9cCMOS IMAGE SENSOR WITH TESTING CIRCUIT FOR VERIFYING OPERATION THEREOFxe2x80x9d filed on Feb. 26, 1999. Therefore, a detailed description will be omitted.
However, the conventional analog-to-digital conversion is carried out by dropping down the reference voltage at a predetermined rate without any consideration of situation. Therefore, it is difficult to adjust the reference voltage level according to various situations such as an offset, light intensity and the like.
It is, therefore, an object of the present invention to provide a CMOS image sensor having a reference voltage controller, in which an erroneous correlated double sampling (CDS) operation is prevented.
In accordance with an embodiment of the present invention, there is provided a CMOS image sensor based on a correlated double sampling method, comprising: a pixel array having Mxc3x97N unit pixels, arranged in a matrix, for sensing an image to generate an analog image data, wherein the analog image data includes a reset voltage level and a data voltage level as an output signal; a ramp voltage generator for generating a updated reference voltage in response to a control signal; a comparator for comparing the reset voltage level with the reference voltage level; a double buffer for storing the digital value; and a reference voltage control means for comparing the reference voltage with the reset voltage level to generate the control signal.